1. Field of the Invention
The invention relates to an integrated content addressable memory (CAM) architecture, and more particularly, to an integrated CAM architecture based on a plurality of novel ten-transistor (10-T) CAM cells combined with a valid bit cell, a protect bit cell, and at least a mask cell coupled to a plurality of associated 10-T CAM cells.
2. Description of the Prior Art
Most memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory accesses. The time required to find an item stored in memory can be reduced significantly if the item can be identified for access by its content rather than by its address. A memory that is accessed in this way is called content-addressable memory (CAM). Briefly speaking, the basic feature of the CAM can be treated as a standard storage system, as a random access memory (RAM) device, combined with a comparison apparatus. Therefore, the CAM is an outgrowth of RAM technology and provides a performance advantage over other memory search structures. The CAM can be used to accelerate any application requiring fast searches of database, lists, or patterns, such as in image, voice recognition, or computer and communication designs. The CAM is also ideally suited for several functions, including data process of the computer""s central processing unit (CPU), Ethernet address lookup, data compression, search engines, pattern recognition for encryption/decryption and compression/decompression applications, and so on.
Conventional content addressable memory (CAM) cells have been implemented primarily with static random access memory (SRAM) cells and arranged in rows and columns. The SRAM-based CAM cells have received widespread use due to the high access speed of SRAM memory cells and the static nature of the cells. With the above-mentioned characteristics of the CAM, in addition to SRAM functions of writing and storing data, the CAM also searches and compares the stored data to determine if the data match a set of compared data (search data) applied to the memory. When the newly applied compared data (search data) match the data already stored in the memory, a match result is indicated, whereas if the search and stored data do not match, a mismatch result is indicated. Please refer to FIG. 1, which is schematic diagram of a typical CAM architecture 10 arranged with a plurality of rows 10A to 10K. As shown in FIG. 1, each row (10A to 10K) is coupled to a corresponding match line 12 (12A to 12K) for indicating whether the compared data match the data stored in the row. The compared data and the previously stored data are all N-bit digital data in the present embodiment. Take row 10A as instance, when the N-bit compared data are totally the same as the N-bit data stored in the row 10A of the CAM architecture 10, the corresponding match line outputs a logic high. On the contrary, when any data bit of the N-bit compared data is opposite to a corresponding data bit of the N-bit data stored in the row of the CAM architecture 10, the corresponding match line changes to output a logic low.
Please go on referring to FIG. 1. Previous approaches regarding data-comparing operation in a row of the CAM architecture 10 include a mask cell 15 (15A to 15K) being coupled to a plurality of associated CAM cells. The comparing operations of the associated CAM cells are then either enabled or disabled by the mask cell 15 (15A to 15K) content. For instance, the mask cell 15A in the row 10A are connected to the associated CAM cells 10A(2) and 10A(3), and the associated CAM cells 10A(2) and 10A (3) can be masked out by the mask cell 15A. Examples of such implementation are also illustrated in U.S. Pat. No. 6,154,384, xe2x80x9cTernary content addressable memory cellxe2x80x9d issued to Nataraj et al. and U.S. Pat. No. 6,108,227, xe2x80x9cContent addressable memory having binary and ternary modes of operationxe2x80x9d issued to Voelkel. Usually the associated CAM cells will be masked out from the comparing operations when the mask cell is asserted, and not be masked out from the comparing operations when the mask cell is de-asserted.
Each row (10A to 10K) comprises a plurality of (binary) CAM cells. For instance, the row 10A comprises N CAM cells 10A(1) to 10A(N). Each CAM cell is able to store a digital data value having two states of information: a logic one state and a logic zero state. As shown in FIG. 1, the N-bit data stored in each row (10A to 10K) consist of N digital data value stored in corresponding N (binary) CAM cells. Please refer to FIG. 2, which is a schematic diagram of a (binary SRAM-based) prior-art CAM cell 20 in a row of the CAM architecture 10 as shown in FIG. 1. Taking the row 10A shown in FIG. 1 for instance, the CAM cell 20 as shown in FIG. 2 can correspond to each of the CAM cells 10A(1) to 10A(N) in the row 10A. The CAM cell 20 includes a SRAM cell 26, a comparator module 24, and a match line 22. The comparator module 24 compares the digital data value stored in the SRAM cell 26 with an input data value. When the input data value is the same as the digital data value stored in the SRAM cell 26, the match line 22 will stay at the pre-charged high level. When the input data value is opposite to the digital data value stored in the SRAM cell 26, the match line 22 will be pulled to a low potential. The CAM cell 20 further includes a word line 28, a first bit line 30, and a second bit line 32, wherein the SRAM cell 26 and the comparator module 24 both share the first and the second bit line 30, 32. Moreover, please refer to both FIG. 1 and FIG. 2, if the CAM cell 20 is in the row 10A and connected to the mask cell 15A as shown in FIG. 1, the CAM cell 20 becomes a mask-able CAM cell 20 that effectively store three states of information, namely: a logic one state, a logic zero state, and a don""t care state for comparing operations. The design of mask-able CAM cells offer more flexibility for users to determine on a row-per-row (entry-per-entry) basis whose partial bits will be masked out during a comparing operation.
For detailing the prior-art embodiment as shown in FIG. 2, please refer to FIG. 3, which is a schematic diagram of a detailed embodiment of the CAM cell 20. The CAM cell 20 is a ten-transistor (10-T) CAM cell 20, which indicates that the SRAM cell 26 is a six-transistor (6-T) SRAM cell 26 and the comparator module 24 is a four-transistor (4-T) comparator module 24. During the practical implementation, the match line 22 will be pre-charged to a predetermined high potential before any comparison between the input data value and the digital data value stored in the 6-T SRAM cell 26. However, due to that the 6-T SRAM cell 26 and the 4-T comparator module 24 share the same first and the second bit line 30 and 32, the pre-charged potential of the match line 22 may be disturbed by the initial state of any other node in the 6-T SRAM cell 26 or the 4-T comparator module 24 as a node N1. In addition, the pre-charged potential of the match line 22 could be pulled down by the charge sharing between the match line 22 and the internal nodes as the node N1, and the voltage drop at the match line 22 depends on the capacitance related to the match line 22 and the internal nodes. All the above-mentioned effects of the prior art will be disadvantageous to the widely applied low-power operations.
In addition, for complying with the trend of integration of multiple functions in one electronic apparatus, it is desirable to keep CAM architecture as powerful as possible without increasing in each cell size that can translate into substantial increases in overall CAM architecture. Therefore, there is a need for developing a novel SRAM-based CAM cell and an integrated CAM architecture that achieve more efficient and sufficient alternatives, including better protection mechanism, larger comparing flexibility, and higher operating speed, than the prior art, while maintaining the characteristics of the SRAM-based CAM cell.
It is therefore a primary objective of the claimed invention to provide a ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture for preventing signal disturbance and for providing integral functions to solve the above-mentioned problems.
In the claimed invention, a novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture are proposed. During implementation, according to the design of 10-T CAM cell of the claimed invention, a pre-charged potential of a match line associated with the 10-T CAM cell will not be disturbed by the initial state of any other node in the 10-T CAM cell. In addition, we provide a valid bit cell and a protect bit cell with a global resetting function in each row (10A to 10K) of the integrated CAM architecture to sufficiently ensure the correction during comparing operations. Combined with the conventional masking operation, the integrated CAM architecture based on the 10-T CAM cells can provide integral and multiple functions to bring the characteristics of CAM into full play.
According to the claimed invention, a ten-transistor (10-T) content addressable memory (CAM) cell comprises a word line: a first bit line; a second bit line; a six-transistor (6-T) static random access memory (SRAM) cell coupled to the word line, the first bit line, and the second bit line for storing a digital data value; a match line for providing a match signal; a third bit line; a fourth bit line; and a four-transistor (4T) comparator module coupled to the match line, the third bit line, the fourth bit line, and the 6-T SRAM cell for comparing the digital data value stored in the 6-T SRAM cell with an input data value provided on the third bit line or the fourth bit line.
According to the claimed invention, an integrated content addressable memory (CAM) comprises a plurality of match lines for providing a plurality of corresponding match signals; and a plurality of rows 10A to 10K, each row coupled to a corresponding match line comprising a plurality of CAM cells coupled to the match line; a valid bit cell coupled to the match line for storing a valid bit indicating whether the row of the integrated CAM contains valid data; and a protect bit cell coupled to the valid bit cell for setting the valid bit to zero when the protect bit cell is de-asserted, and for setting the valid bit intact when the protect bit cell is asserted.
According to the claimed invention, an integrated content addressable memory (CAM) architecture comprises a plurality of match lines for providing a plurality of corresponding match signals; and a plurality of rows, each row coupled to a corresponding match line comprising a plurality of ten-transistor (10-T CAM cells coupled to the corresponding match line, each 10-T CAM cell comprising a word line; a first bit line; a second bit line, wherein the first bit line and the second bit line are a pair of complementary bit lines; a six-transistor (6-T) static random access memory (SRAM) cell coupled to the word line, the first bit line, and the second bit line for storing a digital data value; a first input line; a second input line, wherein the first input line and the second input line are a pair of complementary input lines; and a four-transistor (4-T) comparator module coupled to the match line, the first input line, the second input line, and the 6-T SRAM cell for comparing the digital data value stored in the 6-T SRAM cell with an input data value provided on the first input line or the second input line; a valid bit cell for storing a valid bit indicating whether data stored in the row of the integrated CAM architecture is valid, wherein the data stored in the row of the integrated CAM architecture are composed of the digital data values stored in the 6-T SRAM cells; a protect bit cell coupled to the valid bit cell for setting the valid bit to zero when the protect bit cell is de-asserted, and for setting the valid bit intact when the protect bit cell is asserted; and at least a mask cell coupled to a plurality of associated 10-T CAM cells for masking out the associated 10-T CAM cells when the mask cell is asserted and for not masking out the associated 10-T CAM cells when the mask cell is de-asserted.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.